The present invention relates to information processing systems including processing devices coupled to a main storage memory with dynamic data arrays, and more particularly to means for providing periodic refresh cycles to memory arrays on multiple memory cards comprising main storage.
Dynamic memories are used frequently in data processing systems, as they offer high data storage density at low cost, relative to static memories. Usually, such memories comprise arrays (rows and columns) of individual bit locations or cells. Each cell has a capacitance, and discharges over time, thus giving rise to the need to periodically restore the charge or "refresh" the cell.
The refresh operation involves gaining access individually to each row of a memory array. Arrays typically have multiple rows, e.g. 512 or 1,024 rows. Assuming, for example, that particular arrays must be refreshed every 4 milliseconds and include 512 rows, the refresh cycle, i.e. the time between successive refresh requests, is equal to the refresh interval divided by the number of rows, in this case 0.004 seconds divided by 512 rows or about 7.8 microseconds. The overhead involved in generating and sending these requests substantially reduces memory availability, by up to twenty percent in some cases. This of course diminishes the value of the memory, in terms of its ability to service external requests from processing devices for fetching and storing data.
Attempts to deal with this problem include dividing semiconductor memory into two blocks, for example as disclosed in U.S. Pat. No. 4,106,108 (Cislaghi et al). If a central processor assigns a read/write operation to one of the blocks for a particular cycle, the same cycle is used to refresh a row of memory elements in the other block. A memory divided into two parts also is disclosed in IBM Technical Disclosure Bulletin, Volume 16, No. 3 (August 1973).
Another approach is to delay a memory refresh pulse to service external requests. U.S. Pat. No. 4,691,303 (Churchward et al) discloses a refresh system for multiple banks of semiconductor memory, with logic that prevent refresh pulses from interfering with read/write operations during an initial countdown from a selected value to zero. In U.S. Pat. No. 4,625,301 (Berger), a central processor controlled refresh circuit provides refresh requests that increment a counter, with each refresh operation decrementing the counter. A refresh is forced if the counter reaches a critical limit. IBM Technical Disclosure Bulletin, Volume 25, No. 7A (December 1982) relates to four-bit refresh counter that inhibits the refresh function from count 0000-0111, permits refresh if the memory is not busy from count 1000-1110, and demands a refresh function at count 1111. Each memory cycle time increments the counter, which is reset to zero with each refresh operation.
Other improvements include providing means to select the refresh rate or frequency from among several predefined values, permitting the selection of a single, optimum refresh rate applied to all memory cards. In another known system, a processor provides refresh signals in three groups, which reduces interference due to refresh operations since some memory cards are refreshed while others are available for memory access.
However, for information processing networks with multiple processors contending for a common bus to main storage, in which main storage is made up of multiple memory cards, a processor controlled refreshing of the memory arrays requires substantial time on the common bus, and thus degrades the performance of the network.
Therefore, it is an object of the present invention to provide an information processing network in which dynamic memory arrays are periodically refreshed with minimal interference between refresh cycles and external requests for access to the memory arrays.
Another object of the invention is to transfer some of the intelligence involved in array refresh operations from the processors to the memory cards of main storage.
A further object is to provide a network in which multiple memory cards of main storage can perform refresh operations independently of one another.
Yet another object is to provide a data processing network including means for individually selecting an optimum refresh frequency for each one of multiple memory cards.